Test Your Rig ·

CPU stress

← all tests detecting…
Multi-core score
composite
ready — pick a mode and press Start
Per-core load
Single-core
Multi-core
Scaling
Live
CPU details · estimated
Architecture
Effective clock
L1 cache
L2 cache
L3 cache
WASM SIMD
Cache sizes are inferred from a memory-latency probe (where access time jumps = a cache boundary); clock is inferred from a dependent-op loop. Both are rough estimates affected by the JIT, boost clocks and other load — not vendor specs. The browser can't read the real model/clock/cache.
Mode
Threads
Load
Time